Semiconductor memory, which can be either stand-alone or embedded, commonly has a substantial number of memory locations for storing bits of data. Because integrity of stored data is of major concern, it is usual practice to utilize procedures and hardware that are useful in correcting inaccurate data. More specifically, the potential exists for data to be corrupted during the time that it is stored in memory devices such as by electrical noise or by alpha particles found in memory packaging materials. Electrical noise can also cause data to be corrupted as it is being transferred across conducting lines from one location to another. Because of this possibility, it is necessary to check and correct for such data corruption. In that regard, it is known to use error correction and detection code (ECC) bits. ECC bits are a function of the state or magnitude of the data bits with which they are associated or derived from. ECC bits can be used to detect more than one bit (multiple bit) memory errors. However, common schemes for detecting multiple bit memory errors require the check bits to be stored in memory devices along with data bits, rather than storing all ECC or check bits in a separate device. This constraint related to where ECC bits can be stored relative to normal data bits must be taken into account when testing memory locations in which some of the memory locations store or contain normal data and the other of the memory locations store or contain ECC bits. Additional steps would be required to independently check such memory locations that include a combination of memory locations having normal data and also having ECC bits. That is, a first full test pattern sequence would be used to test a position or subset of the memory locations at a particular address and then a second full test pattern sequence would be used to test the remaining memory locations that were not tested during the first test pattern sequence.
In one known method for testing such memory locations, instead of check bits being generated algorithmically from test data, the states or values of test data themselves are utilized in the testing procedure. Specifically, test data that usually is stored in memory locations for containing normal data is received by and stored in memory locations that are used to store check bits. Such test data written into memory locations intended for check bits is then read. After reading such test check bits from these memory locations intended to store ECC bits, the read data is checked to determine whether or not the check bit memory locations accurately stored and transmitted the expected check bits. If not, an indication is provided that these memory locations for storing ECC or check bits may have one or more faulty memory locations.
Although this known procedure is able to test memory locations for storing check bits using test data, such a procedure lacks certain desirable features related to testing all memory locations, which contain both the test data and the associated check bits, using a single test pattern sequence during a single write operation and a subsequent single read operation. In other words, it would be desirable to test not only the memory locations containing the check bits but also those memory locations containing the test data to which the test check bits are associated, while writing, and some time later reading, data bit locations having a combination of test data and test check bits and without using another or second test pattern sequence to separately test the check bit locations.